On the Limits of Depth Reduction at Depth 3 Over Small Finite Fields
نویسندگان
چکیده
In a surprising recent result, Gupta et.al. [GKKS13b] have proved that over Q any nvariate and n-degree polynomial in VP can also be computed by a depth three ΣΠΣ circuit of size 2 √ n log . Over fixed-size finite fields, Grigoriev and Karpinski proved that any ΣΠΣ circuit that computes the determinant (or the permanent) polynomial of a n× n matrix must be of size 2. In this paper, for an explicit polynomial in VP (over fixed-size finite fields), we prove that any ΣΠΣ circuit computing it must be of size 2 . The explicit polynomial that we consider is the iterated matrix multiplication polynomial of n generic matrices of size n× n. The importance of this result is that over fixed-size fields there is no depth reduction technique that can be used to compute all the n-variate and n-degree polynomials in VP by depth 3 circuits of size 2 . The result of [GK98] can only rule out such a possibility for ΣΠΣ circuits of size 2. We also give an example of an explicit polynomial (NWn,ǫ(X)) in VNP (which is not known to be in VP), for which any ΣΠΣ circuit computing it (over fixed-size fields) must be of size 2 log . The polynomial we consider is constructed from the combinatorial design of Nisan and Wigderson [NW94] and is closely related to the polynomial considered in [KSS13]. An interesting feature of our depth 3 lower bound results is that we provide the first examples of two polynomials (one in VP and one in VNP) such that they have provably stronger circuit size lower bounds than Permanent in a reasonably strong model of computation, i.e. ΣΠΣ circuits over fixed-size finite fields. Next, we explore the depth 4 circuit complexity of the polynomial NWn,ǫ(X) and prove that (over any field) any depth four ΣΠ √ ΣΠ √ n] circuit computing it must be of size 2 √ n log . Before our result, Kayal et.al. [KSS13] showed a depth four 2 √ n logn) circuit size lower bound for an explicit polynomial in VNP and Fournier et.al. [FLMS13] showed a similar circuit size lower bound for a polynomial in VP (which is again the iterated matrix multiplication polynomial). The polynomials considered in [KSS13] and [FLMS13] have a matching depth four ΣΠ √ ΣΠ √ n] circuit size upper bound of 2 √ n . To the best of our knowledge, the polynomial NWn,ǫ(X) is the first example of an explicit polynomial in VNP such that it requires 2 √ n logn) size depth four ΣΠ √ ΣΠ √ n] circuits, but no known matching upper bound.
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ورودعنوان ژورنال:
- Inf. Comput.
دوره 256 شماره
صفحات -
تاریخ انتشار 2014